SN74ACT3651

2048

× 36

CLOCKED FIRST-IN, FIRST-OUT MEMORY

SCAS439D – JUNE 1994 – REVISED FEBRUARY 1999

14

POST OFFICE BOX 655303

tsu(EN)

CLKA

OR

W1

A0 – A35

MBA

ENA

CSA

W/RA

IR

CLKB

CSB

W/RB

MBB

ENB

W1

B0 – B35

tc

th(EN)

tw(CLKH)

tw(CLKL)

th(EN)

tpd(C-OR)

tpd(C-OR)

Old Data in FIFO Output Register

Old Data in FIFO Output Register

ta

12

3

Low

High

tw(CLKL)

tw(CLKH)

High

th(EN)

tsu(EN)

th(D)

tsu(D)

tsk(1)†

tc

Low

High

Low

tsu(EN)

† tsk(1) is the minimum time between a rising CLKA edge and a rising CLKB edge for OR to transition high and to clock the next word to the

FIFO output register in three CLKB cycles. If the time between the rising CLKA edge and rising CLKB edge is less than tsk(1), then the transition

of OR high and the first word load to the output register can occur one CLKB cycle later than shown.

Figure 6. OR-Flag Timing and First-Data-Word Fall Through When the FIFO Is Empty