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V23836-C18-R363 bảng dữ liệu(PDF) 8 Page - Finisar Corporation. |
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V23836-C18-R363 bảng dữ liệu(HTML) 8 Page - Finisar Corporation. |
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8 / 13 page ![]() V23836-C18-R363 Product Specification – October 2006 © Finisar Corporation October 2006 Rev. A Preliminary Data 8 Receiver Electro-Optical Characteristics Values Parameter Symbol min. typ. max. Unit Sensitivity (Average Power)1) 5 V 3.3 V PIN –36 –28 –31 dBm Saturation (Average Power) PSAT –8 dBm Signal Detect Assert Level2) PSDA –34 dBm Signal Detect Deassert Level3) PSDD –44 dBm Signal Detect Hysteresis PSDA–PSDD 1 2 5 dB Signal Detect Assert Time tASS 75 100 µs Signal Detect Deassert Time tDAS 80 350 µs Output Low Voltage4) VOL–VCC –2000 –1580 mV Output High Voltage4) VOH–VCC –1100 –740 mV Output Data Rise/Fall Time, 20% - 80% tR, tF 1.6 ns Output SD Rise/Fall Time 10 40 ns Notes: 1) Minimum average optical power at which the BER is less than 1x10–10 or lower. Measured with a 223–1 NRZPRBS as recommended by ANSI T1E1.2, SONET OC-3 and ITU-T G.957. BOL value –31 dBm max. 2) An increase in optical power of data signal above the specified level will cause the Signal Detect to switch from a low state to a high state. 3) A decrease in optical power of data signal below the specified level will cause the Signal Detect to switch froma high state to a low state. 4) DC/DC, PECL for Signal Detect, PECL compatible. Load is 50Ω into VCC–2 V for data, 510 Ω to VEE for SignalDetect. Measured under DC conditions. For dynamic measurements a tolerance of 50 mV should be added.VCC = 3.3 V. TAMB = 25°C. |
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