GC4014 datasheet(40/46 Pages) TI

40 / 46 page

GRAYCHIP, INC.

- 35 -

APRIL 27, 1999

GC4014 QUAD RECEIVER CHIP

DATA SHEET REV 0.6

This document contains information which may be changed at any time without notice

The suggested DAMPS control register settings for the chip with an input sample rate of 49.7664 MHz

(N=128) is shown in the following table (other input rates can be used up to 62.5 MHz, 49.7664 is used as an

example):

The variables SCALE, BIG_SCALE (address 4) and G (address 16HEX of pages 4,5,6,and 7) are set as

follows. The values of SCALE and BIG_SCALE must be set to satisfy:

. N is

128, so (4log2N) is 28. This means

, which is satisfied by setting SCALE=4 and

BIG_SCALE=4. SCALE, however, needs to be decreased to 3 to prevent overflow in the CFIR, which has a gain of

1.97. The overall gain is set using “G” according to:

Where COARSE is 0 (see Section 7.9) and PFIR_SUM is 240593. The optimal setting of GAIN is 2.0 in order to

compensate for the loss in the tuning process (See Section 7.9). A value of G=18 (12HEX) will give a gain of 2.034.

The output serial format is set in address 6 to have a bit rate of one half the chip’s clock rate and to be used

in the packed mode. The user will need to configure the output format as is necessary for the application.

Table 12: DAMPS Conﬁguration

Control Registers

Channel pages 4,5,6,7

Coefﬁcient Pages

Address

Data

Address

Data

Page 8

Page 9

Page 10

Page 11

00 (HEX)

65 (HEX)1

10 (HEX)

FREQ[0:7]

80->822

FREQ[8:15]

FREQ[16:23]

FREQ[24:31]

00 (HEX)

1P3

read only

1. Initialize to 65 while configuring the chip(s), then set to E5, then back to 65 to fire off the one-shot sync.This

assumes that SO is tied to SI

2. Initialize to 80, then set to 82 after external coefficients are loaded.

3. “P” is the page number. The upper nibble should stay at “1¨.

SCALE

BIG_SCALE

()

4log

–

()

≤

SCALE

BIG_SCALE

() 28

≤

GAIN

128

–

()

{} 2COARSE

[] 1.97

() PFIR_SUM

65536

-------------------

() G

-----





0.113G

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