GC4014 datasheet(15/46 Pages) TI

15 / 46 page

GRAYCHIP, INC.

- 10 -

APRIL 27, 1999

GC4014 QUAD RECEIVER CHIP

DATA SHEET REV 0.6

This document contains information which may be changed at any time without notice

3.6

OUTPUT MODES

The channel or summation outputs are accessible either through internal control registers, through bit serial

outputs, or through nibble serial (link mode) outputs. Note that the bit serial and link mode outputs start, after power

up, in a tri-state condition and must be turned on when the chip is configured.

3.6.1

Internal Control Registers

The internal control registers are loaded by the chip once every output sample period (OSP)1 and held for

the rest of the period. The user is notified that new samples are ready and a new OSP has begun, either through an

interrupt signal provided by the chip’s “READY” pin (RDY/ACK pin), or through a control register bit.

3.6.2

Serial Outputs

The chip provides a bit serial clock (SCK), a frame strobe (SFS) and four data bit lines (SOUT A,B,C and

D) to output the data. A MUX_MODE control specifies whether the four data outputs are transmitted on four separate

bit-serial pins, or multiplexed onto two, or just one pin in a TDM format. Separate output pins are not provided for

the I and Q halves of complex data. The I and Q outputs are always multiplexed onto the same bit-serial pin. The

16 bit I-component is output first, followed by the Q-component. The “packed mode” allows a complex pair to be

treated as a single 32 bit word. The “READY” signal is used to identify the first word of a complex pair or of the TDM

formatted output. The TDM modes are summarized in the following table (See Table 1 for a definition of OUT in the

summation modes):

The bit serial outputs use the format shown in Figure 10. Figure 10(a) shows the standard output mode (the

PACKED mode bit is low). The chip clocks the frame and data out of the chip on the rising edge of SCK (or falling

edge if the SCK_POL bit in the input control register is set). The chip sends the 16 bits (I data first) by setting SFS

high (or low if SFS_POL in the input control register is set) for one clock cycle, and then transmitting the data, MSB

first, on the next 16 clocks. The I/Q data is transmitted “back to back” as shown in Figure 10(a). If the PACKED

control bit is high, then the I and Q components are sent as a single 32 bit word with only one SFS strobe as shown

in Figure 10(b). If two or more channels are multiplexed out the same serial pins, then the subsequent I/Q channel

1. Output sample period (OSP) refers to the interval between output samples at the decimated output rate. For example,

if the input rate (and clock rate) is 10 MHz and the overall decimation factor is 100 (N=25) the OSP will be10

microseconds. An OSP starts when a new sample is ready and stops when the next one is ready.

Table 2: TDM Modes

MUX MODE

SERIAL OUTPUT

AOUT

BOUT

COUT

DOUT

OUTA

OUTB

OUTC

OUTD

OUTA, OUTB

OUTC, OUTD

OUTA, OUTB, OUTC, OUTD

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