LTC2452 datasheet(6/20 Pages) LINER

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LTC2452

2452fb

BLOCK DIAGRAM

PIN FUNCTIONS

SCK (Pin 1): Serial Clock Input. SCK synchronizes the serial

data output. While digital data is available (the ADC is not

in CONVERT state) and CS is LOW (ADC is not in SLEEP

state) a new data bit is produced at the SDO output pin

following every falling edge applied to the SCK pin.

GND (Pin 2): Ground. Connect to a ground plane through

a low impedance connection.

REF (Pin 3): Reference Input. The voltage on REF can have

any value between 2.5V and VCC. The reference voltage

sets the full-scale range.

VCC (Pin 4): Positive Supply Voltage. Bypass to GND

(Pin 2) with a 10μF capacitor in parallel with a low-se-

ries-inductance 0.1μF capacitor located as close to the

LTC2452 as possible.

IN– (Pin 5), IN+ (Pin 6):

Differential Analog Input.

CS (Pin 7): Chip Select (Active LOW) Digital Input. A

LOW on this pin enables the SDO digital output. A HIGH

on this pin places the SDO output pin in a high imped-

ance state.

SDO (Pin 8): Three-State Serial Data Output. SDO is used

for serial data output during the DATA OUTPUT state and

can be used to monitor the conversion status.

Exposed Pad (Pin 9): Ground. Must be soldered to PCB

ground. For prototyping purposes, this pad may remain

ﬂoating.

Figure 1. Functional Block Diagram

16-BIT ΔΣ

A/D CONVERTER

DECIMATING

SINC FILTER

SCK

REF

VCC

GND

IN+

IN–

SDO

2452 BD

–

16-BIT ΔΣ

A/D CONVERTER

SPI

INTERFACE

INTERNAL

OSCILLATOR

2, 9

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