LTC2452 datasheet(13/20 Pages) LINER

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LTC2452

2452fb

sion operation can be triggered by pulling CS low and

then high. When CS is pulled low (CS = LOW), SDO will

output the sign (D15) of the result of the just completed

conversion. While a low logic level is maintained at SCK

pin and CS is subsequently pulled high (CS = HIGH) the

remaining 15 bits of the result (D14:D0) are discarded

and a new conversion cycle starts.

Following the aborted I/O, additional clock pulses in the

CONVERT state are acceptable, but excessive signal tran-

sitions on SCK can potentially create noise on the ADC

during the conversion, and thus may negatively inﬂuence

the conversion accuracy.

2-Wire Operation

The 2-wire operation modes, while reducing the number of

required control signals, should be used only if the LTC2452

low power sleep capability is not required. In addition the

option to abort serial data transfers is no longer available.

Hardwire CS to GND for 2-wire operation.

Figure 13. 2-Wire, Idle-High (CPOL = 1) Serial Clock, Operation Example

Figure 13 shows a 2-wire operation sequence which uses

an idle-high (CPOL = 1) serial clock signal. The conversion

status can be monitored at the SDO output. Following a

conversion cycle, the ADC enters SLEEP state and the

SDO output transitions from HIGH to LOW. Subsequently

16 clock pulses are applied to the SCK input in order

to serially shift the 16 bit result. Finally, the 17th clock

pulse is applied to the SCK input in order to trigger a new

conversion cycle.

Figure 14 shows a 2-wire operation sequence which uses

an idle-low (CPOL = 0) serial clock signal. The conversion

status cannot be monitored at the SDO output. Following

a conversion cycle, the LTC2452 bypasses the SLEEP

state and immediately enters the DATA OUTPUT state. At

this moment the SDO pin outputs the sign (D15) of the

conversion result. The user must use external timing in

order to determine the end of conversion and result avail-

ability. Subsequently 16 clock pulses are applied to SCK

in order to serially shift the 16-bit result. The 16th clock

falling edge triggers a new conversion cycle.

APPLICATIONS INFORMATION

Figure 14. 2-Wire, Idle-Low (CPOL = 0) Serial Clock Operation Example

2452 F13

D15

D14

D13

D12

SD0

clk1

clk2

clk3

clk4

clk15

clk16

clk17

SCK

CONVERT

SLEEP

DATA OUTPUT

CS = LOW

2452 F14

D15

D14

D13

D12

SD0

CS = LOW

clk1

clk2

clk3

clk14

clk4

clk15

clk16

SCK

CONVERT

DATA OUTPUT

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