AX2000-1CS896B datasheet(36/226 Pages) ACTEL

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Axcelerator Family FPGAs

2- 22

v2.7

3.3V LVTTL

Low-Voltage Transistor-Transistor Logic is a general purpose standard (EIA/JESD) for 3.3V applications. It uses an LVTTL

input buffer and push-pull output buffer.

AC Loadings

Timing Characteristics

Table 2-19 • DC Input and Output Levels

VIL

VIH

VOL

VOH

IOL

IOH

Min,V

Max,V

Min,V

Max,V

Min,V

-0.3

0.8

2.0

3.6

0.4

2.4

–24

Figure 2-15 • AC Test Loads

Table 2-20 • AC Waveforms, Measuring Points, and Capacitive Load

Input Low (V)

Input High (V)

Measuring Point* (V)

VREF (typ) (V)

Cload (pF)

3.0

1.40

N/A

* Measuring Point = Vtrip

R to VCCI for tplz/tpzl

R to GND for tphz/tpzh

35 pF for tpzh/tpzl

5 pF for tphz/tplz

Test Point

35 pF

for tristate

R=1k

for tpd

Table 2-21 • 3.3V LVTTL I/O Module

Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 3.0V, TJ = 70°C

'–2' Speed

'–1' Speed

'Std' Speed

Parameter

Description

Min.

Max.

Min.

Max.

Min.

Max.

Units

LVTTL Output Drive Strength = 1 (8mA) / Low Slew Rate

tDP

Input Buffer

1.72

1.96

2.31

tPY

Output Buffer

14.32

16.31

19.19

tICLKQ

Clock-to-Q for the I/O input register

0.67

0.77

0.90

tOCLKQ

Clock-to-Q for the IO output register and the I/O enable

0.67

0.77

0.90

tSUD

Data Input Set-Up

0.23

0.27

0.31

tSUE

Enable Input Set-Up

0.26

0.30

0.35

tHD

Data Input Hold

0.00

tHE

Enable Input Hold

0.00

tCPWHL

Clock Pulse Width High to Low

0.43

0.48

0.57

tCPWLH

Clock Pulse Width Low to High

0.45

0.51

0.60

tWASYN

Asynchronous Pulse Width

0.43

0.48

0.57

tREASYN

Asynchronous Recovery Time

0.10

tHASYN

Asynchronous Removal Time

0.00

tCLR

Asynchronous Clear-to-Q

0.23

0.27

0.31

tPRESET

Asynchronous Preset-to-Q

0.23

0.27

0.31

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