AX2000-1CS896B datasheet(88/226 Pages) ACTEL

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Axcelerator Family FPGAs

2- 74

v2.7

Modes of Operation

There are two read modes and one write mode:

•

Read Nonpipelined (synchronous – one clock edge)

•

Read Pipelined (synchronous – two clock edges)

•

Write (synchronous – one clock edge)

In the standard read mode, new data is driven onto the

RD bus in the clock cycle immediately following RA and

REN valid. The read address is registered on the read-

port active-clock edge and data appears at read-data

after the RAM access time. Setting the PIPE to OFF

enables this mode.

The pipelined mode incurs an additional clock delay

from address to data, but enables operation at a much

higher frequency. The read-address is registered on the

read-port active-clock edge, and the read data is

registered and appears at RD after the second read clock

edge. Setting the PIPE to ON enables this mode.

On the write active-clock edge, the write data are

written into the SRAM at the write address when WEN is

high. The setup time of the write address, write enables,

and write data are minimal with respect to the write

clock.

Write and read transfers are described with timing

requirements beginning in "Timing Characteristics".

Timing Characteristics

Figure 2-58 • SRAM Model

Figure 2-59 • RAM Write Timing Waveforms

REN

WCLK

RCLK

WEN

WCLK

tWCKP

tWxxSU

tWxxHD

tWCKH

tWCKL

WA<11:0>, WD<35:0>, WEN<4:0>

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