AX2000-1CSG896B datasheet(62/226 Pages) ACTEL

tên linh kiện	AX2000-1CSG896B

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Axcelerator Family FPGAs

2- 48

v2.7

Timing Models and Waveforms

Timing Characteristics

Figure 2-32 • R-Cell Delays

CLR

PRESET

CLK

tSUE

tHE

tSUD

tHD

tRCO

tWASYN

tHASYN

tCLR

tREASYN

tCPWHL

tCPWLH

tPRESET

tWASYN

tHASYN

tREASYN

Table 2-62 • R-Cell

Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 3.0V, TJ = 70°C

'–2' Speed

'–1' Speed

'Std' Speed

Parameter

Description

Min.

Max.

Min.

Max.

Min.

Max.

Units

R-Cell Propagation Delays

tRCO

Sequential Clock-to-Q

0.67

0.77

0.90

tCLR

Asynchronous Clear-to-Q

0.23

0.27

0.31

tPRESET

Asynchronous Preset-to-Q

0.23

0.27

0.31

tSUD

Flip-Flop Data Input Set-Up

0.23

0.27

0.31

tSUE

Flip-Flop Enable Input Set-Up

0.26

0.30

0.35

tHD

Flip-Flop Data Input Hold

0.00

tHE

Flip-Flop Enable Input Hold

0.00

tWASYN

Asynchronous Pulse Width

0.43

0.48

0.57

tREASYN

Asynchronous Recovery Time

0.10

tHASYN

Asynchronous Removal Time

0.00

tCPWHL

Clock Pulse Width High to Low

0.42

0.47

0.55

tCPWLH

Clock Pulse Width Low to High

0.40

0.46

0.54

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