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A32100DX-PLB bảng dữ liệu(PDF) 46 Page - Actel Corporation

tên linh kiện A32100DX-PLB
Giải thích chi tiết về linh kiện  Integrator Series FPGAs: 1200XL and 3200DX Families
PDF  84 Pages
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nhà sản xuất  ACTEL [Actel Corporation]
Trang chủ  http://www.actel.com
Logo ACTEL - Actel Corporation

A32100DX-PLB bảng dữ liệu(HTML) 46 Page - Actel Corporation

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Inte gra t or Serie s FP GAs: 1 200XL a nd 3200 DX F amilie s
46
Discontinued – v3.0
A321 40DX Timing Char act eristics (continued)
(Worst-Case Commercial Conditions VCC = 4.75 V, TJ = 70°C)
‘–2 Speed
‘–1’ Speed
‘Std’ Speed
‘–F’ Speed
3.3V ‘Std’
Speed
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Units
TTL Output Module Timing1
tDLH
Data-to-Pad High
3.3
4.4
5.1
6.7
6.0
ns
tDHL
Data-to-Pad Low
3.5
4.6
5.4
7.1
6.3
ns
tENZH
Enable-Pad Z to High
4.1
5.5
6.4
8.4
7.5
ns
tENZL
Enable-Pad Z to Low
4.4
5.9
6.9
9.0
8.1
ns
tENHZ
Enable-Pad High to Z
7.1
9.5
11.1
14.5
13.0
ns
tENLZ
Enable-Pad Low to Z
7.1
9.5
11.1
14.5
13.0
ns
tGLH
G-to-Pad High
6.5
8.7
10.2
13.3
12.0
ns
tGHL
G-to-Pad Low
6.5
8.7
10.2
13.3
12.0
ns
tLSU
I/O Latch Output Set-Up
0.4
0.6
0.7
0.9
0.82
ns
tLH
I/O Latch Output Hold
0.0
0.0
0.0
0.0
0.0
ns
tLCO
I/O Latch Clock-Out (Pad-to-Pad) 32 I/O
8.4
11.1
13.1
17.0
15.4
ns
tACO
Array Latch Clock-Out (Pad-to-Pad) 32 I/O
11.8
15.7
18.5
24.1
21.7
ns
dTLH
Capacitive Loading, Low to High
0.03
0.04
0.05
0.07
0.06
ns/pF
dTHL
Capacitive Loading, High to Low
0.02
0.03
0.07
0.1
0.08
ns/pF
tWDO
Hard-Wired Wide-Decode Output
0.03
0.04
0.05
0.07
0.06
ns/pF
CMOS Output Module Timing1
tDLH
Data-to-Pad High
3.5
4.6
5.4
7.1
6.0
ns
tDHL
Data-to-Pad Low
3.3
4.4
5.1
6.7
6.3
ns
tENZH
Enable-Pad Z to High
4.1
5.5
6.4
8.4
7.5
ns
tENZL
Enable-Pad Z to Low
4.4
5.9
6.9
9.0
8.1
ns
tENHZ
Enable-Pad High to Z
7.1
9.5
11.1
14.5
13.0
ns
tENLZ
Enable-Pad Low to Z
7.1
9.5
11.1
14.5
13.0
ns
tGLH
G-to-Pad High
6.5
8.7
10.2
13.3
12.0
ns
tGHL
G-to-Pad Low
6.5
8.7
10.2
13.3
12.0
ns
tLSU
I/O Latch Set-Up
0.4
0.6
0.7
0.9
0.82
ns
tLH
I/O Latch Hold
0.0
0.0
0.0
0.0
0.0
ns
tLCO
I/O Latch Clock-Out (Pad-to-Pad) 32 I/O
9.9
13.3
15.6
20.3
18.3
ns
tACO
Array Latch Clock-Out (Pad-to-Pad) 32 I/O
13.9
18.5
21.8
28.3
25.6
ns
dTLH
Capacitive Loading, Low to High
0.04
0.06
0.07
0.1
0.08
ns/pF
dTHL
Capacitive Loading, High to Low
0.04
0.05
0.06
0.1
0.07
ns/pF
tWDO
Hard-Wired Wide-Decode Output
0.3
0.4
0.5
0.7
0.6
ns/pF
Note:
1.
Delays based on 35 pF loading.



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