CoreAI

12

v2.0

Table 10 • ACM Control/Status Register (low-order)

Bits

Name

Function

7:5

Reserved

Not used

4

ACMWRBUSY

ACM Write Cycle Busy (read-only) – If 1, the ACM is busy writing data into the AB block.

3

ACMRDBUSY

ACM Read Cycle Busy (read-only) – If 1, the ACM is busy reading data from the AB block.

2

ACMRESETBUSY

ACM Reset Cycle Busy (read-only) – If 1, the ACM is busy being reset.

1

ACMRDSTART

ACM Read Start (write-only)

1 – The ACM starts a read cycle from the ACM address in the ACMADDR[7:0] bits of the ACM

Address/Data register. Note that this write-only bit is active for one ACM clock cycle (self-clearing),

and that the resulting busy signal from the ACM read taking place will be reflected in the

ACMRDBUSY bit of this register.

0 – Normal (no operation or current ACM operation continues)

0

ACMRESET

ACM Reset (write-only)

1 – The ACM is put into a reset condition. Note that this write-only bit is active for only one ACM

clock cycle (self-clearing), and that the resulting busy signal from the ACM reset taking place will

be reflected in the ACMRESETBUSY bit of this register.

0 – Normal (no operation or current ACM operation continues)

Table 11 • ACM Control/Status Register (high-order)

Bits

Name

Function

7:0

Reserved

Not used

Table 12 • ACM Address Register

Bits

Name

Function

7:0

ACMADDR[7:0]

ACM Address

These bits are connected to the ACMADDR[7:0] port of the AB macro.

(Refer to the

Fusion datasheet for further information.)

Table 13 • ACM Data Register

Bits

Name

Function

7:0

ACMDATA[7:0]

ACM Data

If this register is read from, the ACMRDATA[7:0] output port from the AB block is returned.

If this register is written to, it will drive the ACMWDATA[7:0] input port of the AB block.