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XIO2000AI bảng dữ liệu(PDF) 98 Page - TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS

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Giải thích chi tiết về linh kiện  PCI Express to PCI Bus Translation Bridge
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Classic PCI Configuration Space
88
April 2007 Revised October 2008
SCPS155C
4.68 Clock Run Status Register
The clock run status register indicates the state of the PCI clock-run features in the bridge. See Table 4−42
for a complete description of the register contents.
PCI register offset:
DAh
Register type:
Read-only
Default value:
00h
BIT NUMBER
7
6
5
4
3
2
1
0
RESET STATE
0
0
0
0
0
0
0
0
Table 4−42. Clock Run Status Register Description
BIT
FIELD NAME
ACCESS
DESCRIPTION
7:1
RSVD
R
Reserved. Returns 000 0000b when read.
0†
SEC_CLK_STATUS
RU
Secondary clock status. This bit indicates the status of the PCI bus secondary clock outputs.
0 = Secondary clock running
1 = Secondary clock stopped
† This bit is reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.



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