AT52SC1283J datasheet(30/52 Pages) ATMEL

30 / 52 page

3530B–STKD–2/4/05

AT52SC1283J/1284J [Preliminary]

19. AVD Pulsed Asynchronous Read Cycle Waveform

(1)(2)

Notes:

1. After the high-to-low transition on AVD, AVD may remain low as long as the address is stable.

2. CLK may be static high or static low.

20. Asynchronous Read Cycle Waveform

(1)(2)(3)(4)

Notes:

1. CE may be delayed up to t

ACC - tCE after the address transition without impact on tACC.

2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change

without impact on t

ACC.

3. t

DF is specified from OE or CE, whichever occurs first (CL = 5 pF).

4. AVD and CLK should be tied low.

18. AC Asynchronous Read Timing Characteristics

Symbol

Parameter

Min

Max

Units

ACC1

Access, AVD To Data Valid

tACC2

Access, Address to Data Valid

Access, CE to Data Valid

OE to Data Valid

tAHAV

Address Hold from AVD

9ns

AVLP

AVD Low Pulse Width

AVHP

AVD High Pulse Width

tAAV

Address Valid to AVD

7ns

CE, OE High to Data Float

Output Hold from OE, CE or Address, Whichever Occurred First

tRO

RESET to Output Delay

150

tCE

tACC2

tDF

tAHAV

DATA VALID

I/O0-I/O15

A2 -A22

tAAV

tAVLP

tACC1

AVD

tOE

tAVHP

RESET

tRO

(1)

tACC2

tAHAV

A0 -A1

tAAV

OUTPUT

VALID

I/O0 - I/O15

HIGH Z

RESET

tOE

tCE

ADDRESS VALID

tDF

tOH

tACC2

tRO

A0 - A22

tRC

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