ATA5425-PLSW datasheet(79/100 Pages) ATMEL

79 / 100 page

4841D–WIRE–10/07

ATA5423/ATA5425/ATA5428/ATA5429

4.11 External CLK frequency

RF = 315 MHz

CLK division ratio = 3

CLK has nominal 50%

duty cycle

CLK

4.244

MHz

fRF = 345 MHz

CLK division ratio = 3

CLK has nominal 50%

duty cycle

CLK

4.648

MHz

RF = 433.92 MHz

CLK division ratio = 3

CLK has nominal 50%

duty cycle

CLK

4.418

MHz

RF = 868.3 MHz

CLK division ratio = 3

CLK has nominal 50%

duty cycle

CLK

4.471

MHz

RF = 915 MHz

CLK division ratio = 3

CLK has nominal 50%

duty cycle

fCLK

4.711

MHz

4.12 DC voltage after start

-up

VDC(XTAL1, XTAL2)

XTO running

(IDLE mode, RX mode

and TX mode)

24, 25

VDCXTO

–150

–30

12. Electrical Characteristics: General (Continued)

This device is manufactured with an industrial (not automotive) grade process and process controls. Although this device may

meet certain automotive grade criteria in performance, Atmel can not recommend that this device be used in any automotive

application.

All parameters refer to GND and are valid for Tamb = 25°C, VVS1 = VVS2 = 3.0V (1-battery application), VVS2 = 6.0V (2-battery application)

and VVS2 = VVAUX = 5.0V (Base-station Application). Typical values are given at fRF = 433.92 MHz unless otherwise specified. Details

about current consumption, timing and digital pin properties can be found in the specific sections of the “Electrical Characteristics”.

No. Parameters

Test Conditions

Pin(1)

Symbol

Min.

Typ.

Max.

Unit

Type*

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

Note:

1. Pin numbers in brackets mean they were measured with RF_IN matched to 50

Ω according to Figure 3-1 on page 11 with

component values according to Table 3-2 on page 12 and RF_OUT matched to 50

Ω according to Figure 3-10 on page 21

with component values according to Table 3-7 on page 22.

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