ACS8946 datasheet(21/40 Pages) SEMTECH

21 / 40 page

ADVANCED COMMUNICATIONS

FINAL

DATASHEET

Revision 3/November 2006 © Semtech Corp.

Page 21

www.semtech.com

ACS8946 JAM PLL

Output Jitter

The output jitter meets all requirements of ITU, Telcordia

and ETSI standards for SONET rates up to 622.08 MHz

(OC-12/STM-4). See the “Electrical Specifications”

sections for details on the jitter figures across the

different output jitter frequency bands relevant to each

specification.

The recommended bandwidth of around 2 kHz is suitable

for both meeting the specification on output jitter

generation requirements and for filtering out the input

jitter from the input clock.

System Reset

After power-up or a system reset via the RESETB (pin 40),

the internal control logic waits for the presence of an input

signal of approximately the correct frequency (at least

40% of the nominal) and then allows a further settling

time of 60 ms before allowing internal frequency tuning,

frequency-locking and phase-locking on to the input clock.

Consequently reset should be removed only when the

input frequency is within 400 ppm of the nominal

frequency.

Layout Recommendations

It is highly recommended to use a stable and filtered 3.3 V

power supply to the device. A separate filtered power and

ground plane is recommended with supply decoupling

capacitors of 10 nF and 100 pF utilizing good high

frequency chip capacitors (0402 or 0603 format surface-

mount package) on each VDD. Good differential signal

layout on the input and output lines should be used to

ensure matched track impedance and phase. Contact

Semtech directly for further layout recommendations.

ALARM2_CO1

ALARMC_CO3

62.50

31.25

7.81

3.91

CFG_OUT2

GND

62.50

31.25

7.81

Off

CFG_OUT2

VDD

62.50

31.25

3.91

Off

CFG_OUT2

ALARM1_CO0

62.50

15.63

7.81

3.91

CFG_OUT2

ALARM2_CO1

62.50

15.63

7.81

Off

CFG_OUT2

62.50

15.63

3.91

Off

CFG_OUT2

ALARMC_CO3

62.50

7.81

3.91

Off

ALARMC_CO3

GND

31.25

15.63

7.81

3.91

ALARMC_CO3

VDD

31.25

15.63

7.81

Off

ALARMC_CO3

ALARM1_CO0

31.25

15.63

3.91

Off

ALARMC_CO3

ALARM2_CO1

31.25

7.81

3.91

Off

ALARMC_CO3

CFG_OUT2

15.63

7.81

3.91

Off

Note: (i) Odd divider = 5 (see Table 13)

Table 15 Output Configuration and Selection for Ethernet Rates (156.25 MHz or 125 MHz input) (cont...)

Row no.

Wiring of Configuration Pins

“Available Rates” and Associated “AB” Values (See Note (i))

CFG_IN0

CFG_IN1

AB = 11

AB = 10

AB = 01

AB = 00

ACS8946 bảng dữ liệu(PDF) 21 Page - Semtech Corporation

ACS8946 bảng dữ liệu(HTML) 21 Page - Semtech Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

bảng dữ liệu tải về

Link URL