3

3672A–CNFG–1/08

AT18F010/002/040/080 [Preliminary]

4.

Device Description

The download interface of the configuration memory will directly communicate with the FPGA

through the interface-control signals (CLK, RESET/OE, CE) to initialize and terminate configura-

tion. All FPGA devices in the master serial mode can control the entire configuration process to

receive data from the configuration device without requiring an external intelligent controller.

When FPGA devices are used in slave serial mode, an external clock signal can be applied to

the CLK pin of an AT18F series device as a configuration loading clock. Multiple FPGAs that are

setup in Master Serial and Slave Serial modes can also be used to control the configuration pro-

cess to obtain data from a single configurator or cascaded configurators. Please contact Atmel

at configurator@atmel.com for detailed descriptions.

The CF pin is used as an optional input pin for the JTAG CONFIG instruction to initialize the

FPGA configuration without requiring powering down the device. The RESET/OE and CE pins

control the tri-state buffer on the DATA output pin and enable the address counter. When

RESET/OE is driven Low, the configuration device resets its address counter and tri-states its

DATA pin. The CE pin also controls the output of the AT18F Series Configurator. If CE is held

High after the RESET/OE reset pulse, the counter is reset and the DATA output pin is tri-stated.

When the configurator has driven out all of its data and CEO is driven Low, the device tri-states

the DATA pin to avoid contention with other configurators. Upon power-up, the address counter

is automatically reset.