8

3672A–CNFG–1/08

AT18F010/002/040/080 [Preliminary]

8.

Configuration Memory to FPGA Device Interface Connection Diagrams

Figure 8-1.

General Connection Diagram for Loading FPGA from Configurator and JTAG Signals

Notes:

1. Signals within parenthesis will be applied to Atmel AT40AK FPGA.

2. For details of the circuit connection, please contact factory.