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ATF1504ASL bảng dữ liệu(PDF) 12 Page - ATMEL Corporation

tên linh kiện ATF1504ASL
Giải thích chi tiết về linh kiện  Highperformance Complex Programmable Logic Device
PDF  35 Pages
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nhà sản xuất  ATMEL [ATMEL Corporation]
Trang chủ  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

ATF1504ASL bảng dữ liệu(HTML) 12 Page - ATMEL Corporation

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ATF1504AS(L)
0950O–PLD–7/05
Absolute Maximum Ratings*
Temperature Under Bias.................................. -40°C to +85°C
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Note:
1.
Minimum voltage is -0.6V DC, which may under-
shoot to -2.0V for pulses of less than 20 ns. Max-
imum output pin voltage is V
CC + 0.75V DC,
which may overshoot to 7.0V for pulses of less
than 20 ns.
Storage Temperature ..................................... -65°C to +150°C
Voltage on Any Pin with
Respect to Ground .........................................-2.0V to +7.0V(1)
Voltage on Input Pins
with Respect to Ground
During Programming.....................................-2.0V to +14.0V(1)
Programming Voltage with
Respect to Ground .......................................-2.0V to +14.0V(1)
AC Characteristics
Symbol
Parameter
-7
-10
-15
-20
-25
Units
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
t
PD1
Input or Feedback to
Non-registered Output
7.5
10
3
15
20
25
ns
tPD2
I/O Input or Feedback to
Non-registered Feedback
79
3
12
16
25
ns
tSU
Global Clock Setup Time
6
7
11
16
20
ns
t
H
Global Clock Hold Time
0
0
0
0
0
ns
t
FSU
Global Clock Setup Time of
Fast Input
33
3
3
5
ns
t
FH
Global Clock Hold Time of
Fast Input
0.5
0.5
1.0
1.5
2
ns
t
COP
Global Clock to Output Delay
4.5
5
8
10
13
ns
t
CH
Global Clock High Time
3
4
5
6
7
ns
tCL
Global Clock Low Time
3
4
5
6
7
ns
t
ASU
Array Clock Setup Time
3
3
4
4
5
ns
t
AH
Array Clock Hold Time
2
3
4
5
6
ns
tACOP
Array Clock Output Delay
7.5
10
15
20
25
ns
t
ACH
Array Clock High Time
3
4
6
8
10
ns
t
ACL
Array Clock Low Time
3
4
6
8
10
ns
tCNT
Minimum Clock Global Period
8
10
13
17
22
ns
fCNT
Maximum Internal Global
Clock Frequency
125
100
76.9
66
50
MHz
tACNT
Minimum Array Clock Period
8
10
13
17
22
ns
fACNT
Maximum Internal Array
Clock Frequency
125
100
76.9
66
50
MHz



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