CS43L22 datasheet(42/68 Pages) CIRRUS

tên linh kiện	CS43L22

Giải thích chi tiết về linh kiện	Low Power, Stereo DAC w/Headphone & Speaker Amps

PDF	68 Pages

Scroll/Zoom	100%

nhà sản xuất	CIRRUS [Cirrus Logic]

Trang chủ	http://www.cirrus.com

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42 / 68 page

DS792F1

CS43L22

Confidential Draft

10/7/08

7.5.5

Audio Word Length

Configures the audio sample word length used for the data into SDIN.

Note:

When the internal MCLK/LRCK ratio is set to 125 in Master Mode, the 32-bit data width option

for DSP Mode is not valid unless SCLK=MCLK.

7.6

Interface Control 2 (Address 07h)

7.6.1

SCLK equals MCLK

Configures the SCLK signal source for Master Mode.

Note:

This bit is only valid for MCLK = 12.0000 MHz.

7.6.2

Speaker/Headphone Switch Invert

Determines the control signal polarity of the SPK/HP_SW pin.

AWL[1:0]

Audio Word Length

DSP Mode

Right Justified

32-bit data

24-bit data

20-bit data

18-bit data

16-bit data

Application:

“DSP Mode” on page 32

Reserved

SCLK=MCLK

Reserved

INV_SWCH

Reserved

SCLK=MCLK

Output SCLK

Re-timed signal, synchronously derived from MCLK

Non-retimed, MCLK signal

INV_SWCH

SPK/HP_SW pin 6 Control

Not inverted

Inverted

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