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PCF8576DT/2 bảng dữ liệu(PDF) 18 Page - NXP Semiconductors

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Giải thích chi tiết về linh kiện  Universal LCD driver for low multiplex rates
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PCF8576DT/2 bảng dữ liệu(HTML) 18 Page - NXP Semiconductors

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PCF8576D_7
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 7 — 18 December 2008
18 of 52
NXP Semiconductors
PCF8576D
Universal LCD driver for low multiplex rates
In the 1:4 mode, the eight transmitted data bits are placed in bits 0, 1, 2 and 3 of two
successive display RAM addresses.
7.11 Data pointer
The addressing mechanism for the display RAM is realized using the data pointer. This
allows the loading of an individual display data byte, or a series of display data bytes, into
any location of the display RAM. The sequence commences with the initialization of the
data pointer by the load-data-pointer command (see Section 7.17). Following this, an
arriving data byte is stored at the display RAM address indicated by the data pointer in
accordance with the filling order shown in Figure 12. After each byte is stored, the
contents of the data pointer are automatically incremented by a value dependent on the
selected LCD drive mode: eight (static drive mode), four (1:2 mode), three (1:3 mode) or
two (1:4 mode). If an I2C-bus data access is terminated early then the state of the data
pointer will be unknown. The data pointer should be re-written prior to further RAM
access.



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