LPC2292 datasheet(11/53 Pages) NXP

11 / 53 page

LPC2292_2294_7

Product data sheet

Rev. 7 — 4 December 2008

11 of 53

NXP Semiconductors

LPC2292/LPC2294

16/32-bit ARM microcontrollers with external memory interface

P1[25]/EXTIN0

60[7]

K8[7]

EXTIN0 — External Trigger Input. Standard I/O with internal

pull-up.

P1[26]/RTCK

52[7]

N6[7]

I/O

RTCK — Returned Test Clock output. Extra signal added to

the JTAG port. Assists debugger synchronization when

processor frequency varies. Bidirectional pin with internal

pull-up.

Note: LOW on this pin while RESET is LOW, enables pins

P1[31:26] to operate as Debug port after reset.

P1[27]/TDO

144[7]

B2[7]

TDO — Test Data out for JTAG interface.

P1[28]/TDI

140[7]

A3[7]

TDI — Test Data in for JTAG interface.

P1[29]/TCK

126[7]

A7[7]

TCK — Test Clock for JTAG interface. This clock must be

slower than 1

⁄

6 of the CPU clock (CCLK) for the JTAG interface

to operate.

P1[30]/TMS

113[7]

D10[7]

TMS — Test Mode Select for JTAG interface.

P1[31]/TRST

43[7]

M4[7]

TRST — Test Reset for JTAG interface.

P2[0] to P2[31]

I/O

Port 2 — Port 2 is a 32-bit bidirectional I/O port with individual

direction controls for each bit. The operation of port 2 pins

depends upon the pin function selected via the Pin Connect

Block.

P2[0]/D0

98[7]

E12[7]

I/O

D0 — External memory data line 0.

P2[1]/D1

105[7]

C12[7]

I/O

D1 — External memory data line 1.

P2[2]/D2

106[7]

C11[7]

I/O

D2 — External memory data line 2.

P2[3]/D3

108[7]

B12[7]

I/O

D3 — External memory data line 3.

P2[4]/D4

109[7]

A13[7]

I/O

D4 — External memory data line 4.

P2[5]/D5

114[7]

C10[7]

I/O

D5 — External memory data line 5.

P2[6]/D6

115[7]

B10[7]

I/O

D6 — External memory data line 6.

P2[7]/D7

116[7]

A10[7]

I/O

D7 — External memory data line 7.

P2[8]/D8

117[7]

D9[7]

I/O

D8 — External memory data line 8.

P2[9]/D9

118[7]

C9[7]

I/O

D9 — External memory data line 9.

P2[10]/D10

120[7]

A9[7]

I/O

D10 — External memory data line 10.

P2[11]/D11

124[7]

A8[7]

I/O

D11 — External memory data line 11.

P2[12]/D12

125[7]

B7[7]

I/O

D12 — External memory data line 12.

P2[13]/D13

127[7]

C7[7]

I/O

D13 — External memory data line 13.

P2[14]/D14

129[7]

A6[7]

I/O

D14 — External memory data line 14.

P2[15]/D15

130[7]

B6[7]

I/O

D15 — External memory data line 15.

P2[16]/D16

131[7]

C6[7]

I/O

D16 — External memory data line 16.

P2[17]/D17

132[7]

D6[7]

I/O

D17 — External memory data line 17.

P2[18]/D18

133[7]

A5[7]

I/O

D18 — External memory data line 18.

P2[19]/D19

134[7]

B5[7]

I/O

D19 — External memory data line 19.

P2[20]/D20

136[7]

D5[7]

I/O

D20 — External memory data line 20.

P2[21]/D21

137[7]

A4[7]

I/O

D21 — External memory data line 21.

P2[22]/D22

1[7]

A1[7]

I/O

D22 — External memory data line 22.

P2[23]/D23

10[7]

E3[7]

I/O

D23 — External memory data line 23.

Table 4.

Pin description …continued

Symbol

Pin (LQFP)

(TFBGA)[1]

Type

Description

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