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MPC8640DEC bảng dữ liệu(PDF) 111 Page - Freescale Semiconductor, Inc |
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MPC8640DEC bảng dữ liệu(HTML) 111 Page - Freescale Semiconductor, Inc |
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111 / 140 page ![]() MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 111 Clocking 18.3 e600 to MPX clock PLL Ratio Table 68 describes the clock ratio between the platform and the e600 core clock. This ratio is determined by the binary value of LDP[0:3], LA[27](cfg_core_pll[0:4] - reset config name) at power up, as shown in Table 68. 18.4 Frequency Options 18.4.1 SYSCLK to Platform Frequency Options Table 69 shows some SYSCLK frequencies and the expected MPX frequency values based on the MPX clock to SYSCLK ratio. Note that frequencies between 400 MHz and 500 MHz are NOT supported on the 0010 2:1 0011 3:1 0100 4:1 0101 5:1 0110 6:1 0111 Reserved 1000 8:1 1001 Reserved Table 68. e600 Core to MPX Clock Ratio Binary Value of LDP[0:3], LA[27] Signals e600 core: MPX Clock Ratio 01000 2:1 01100 2.5:1 10000 3:1 11100 Reserved 10100 Reserved 01110 Reserved Table 67. MPX:SYSCLK Ratio Binary Value of LA[28:31] Signals MPX:SYSCLK Ratio |
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