MPC8640DEC datasheet(109/140 Pages) FREESCALE

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MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

109

Clocking

S3. This pin should be pulled to GND for the single core device.

S4. No special requirement for this pin on single core device. Pin should be tied to power supply as directed for dual core.

18 Clocking

This section describes the PLL configuration of the MPC8640. Note that the platform clock is identical to

the MPX clock.

18.1

Clock Ranges

Table 63 provides the clocking specifications for the processor cores and Table 64 provides the clocking

specifications for the memory bus. Table 65 provides the clocking for the Platform/MPX bus and Table 66

provides the clocking for the Local bus.

Table 63. Processor Core Clocking Specifications

Characteristic

Maximum Processor Core Frequency

Unit

Notes

1000 MHz

1067 MHz

1250MHz

Min

Max

Min

Max

Min

Max

e600 core processor frequency

800

1000

800

1067

800

1250

MHz

1, 2

Notes:

1. Caution: The MPX clock to SYSCLK ratio and e600 core to MPX clock ratio settings must be chosen such

that the resulting SYSCLK frequency, e600 (core) frequency, and MPX clock frequency do not exceed their

respective maximum or minimum operating frequencies. Refer to Section 18.2, “MPX to SYSCLK PLL Ratio,”

and Section 18.3, “e600 to MPX clock PLL Ratio,” for ratio settings.

2. The minimum e600 core frequency is based on the minimum platform clock frequency of 400 MHz.

Table 64. Memory Bus Clocking Specifications

Characteristic

Maximum Processor Core

Frequency

Unit

Notes

1000, 1067, 1250 MHz

Min

Max

Memory bus clock frequency

200

266

MHz

1, 2

Notes:

1. Caution: The MPX clock to SYSCLK ratio and e600 core to MPX clock ratio settings must be

chosen such that the resulting SYSCLK frequency, e600 (core) frequency, and MPX clock

frequency do not exceed their respective maximum or minimum operating frequencies. Refer to

Section 18.2, “MPX to SYSCLK PLL Ratio,” and Section 18.3, “e600 to MPX clock PLL Ratio,” for

ratio settings.

2. The memory bus clock speed is half the DDR/DDR2 data rate, hence, half the MPX clock

frequency.

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