TMS320C6745PTP2 datasheet(49/203 Pages) TI

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4.6.4

CFGCHIP3

TMS320C6745/6747 Floating-point Digital Signal Processor

www.ti.com

SPRS377B – SEPTEMBER 2008 – REVISED DECEMBER 2008

Table 4-7. CFGCHIP2 Field Description (continued)

Bit

Field

Description

3:0

USB0REF-FREQ[3:0]

USB0 Phy Clock Input Select.

0000 = Reserved

0001 = 12 MHz

0010 = 24 MHz

0011 = 48 MHz

0100 = 19.2 MHz

0101 = 38.4 MHz

0110 = 13 MHz

0111 = 26 MHz

1000 = 20 MHz

1001 = 40 MHz

1010 = Reserved

1011 = Reserved

1100 = Reserved

1101 = Reserved

1110 = Reserved

1111 = Reserved

Reserved

R-n/a

Reserved

DIV4P5EN

EMA_CL

EMB_C

KSRC

LKSRC

R/W-1

R/W-0

LEGEND: R = Read, W = Write, n = value at reset

Figure 4-7. CFGCHIP3 Register Bit Layout

Table 4-8. CFGCHIP3 Field Description

Bit

Field

Description

31:16

Reserved

15:8

Reserved

7:3

Reserved

DIV4P5ENA

Fixed 4.5 divider Enable.

0 = Divide by 4.5 is Disabled. 1 = Divide by 4.5 is Enabled.

EMA_CLKSRC

EMIF A Memory Clock Source Select.

0 = EMIFA clock domain is driven by the PLLCTRL SYSCLK3 output.

1 = EMIFA clock domain is driven by the fixed / 4.5 PLL output.

EMB_CLKSRC

EMIF B Memory Clock Source Select.

0 = EMIFB SDRAM clock domain is driven by the PLLCTRL SYSCLK5 output.

1 = EMIFB SDRAM clock domain is driven by the fixed / 4.5 PLL output.

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