TDA9115 datasheet(23/45 Pages) STMICROELECTRONICS

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TDA9115

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9 - OPERATING DESCRIPTION

9.1 SUPPLY AND CONTROL

9.1.1 Power supply and voltage references

The device is designed for a typical value of power

supply voltage of 12 V.

In order to avoid erratic operation of the circuit at

power supply ramp-up or ramp-down, the value of

VCC is monitored. See Figure 1 and electrical

specifications. At switch-on, the device enters a

“normal operation” as the supply voltage exceeds

VCCEn and stays there until it decreases below

VCCDis. The two thresholds provide, by their differ-

ence, a hysteresis to bridge potential noise. Out-

side the “normal operation”, the signals on HOut,

BOut and VOut outputs are inhibited and the I2C

bus interface is inactive (high impedance on SDA,

SCL pins, no ACK), all I2C bus control registers

being reset to their default values (see chapter I2C

BUS CONTROL REGISTER MAP on page 20).

Figure 1. Supply voltage monitoring

Internal thresholds in all parts of the circuit are de-

rived from a common internal reference supply

VRefO that is lead out to RefOut pin for external fil-

tering against ground as well as for external use

with load currents limited to IRefO. The filtering is

necessary to minimize interference in output sig-

nals, causing adverse effects like e.g. jitter.

9.1.2 I2C Bus Control

The I2C bus is a 2 line bi-directional serial commu-

nication bus introduced by Philips. For its general

description, refer to corresponding Philips I2C bus

specification.

This device is an I2C bus slave, compatible with

fast (400kHz) I

2C bus protocol, with write mode

slave address of 8C. Integrators are employed at

the SCL (Serial Clock) input and at the input buffer

of the SDA (Serial Data) input/output to filter off the

spikes of up to 50ns.

The device supports multiple data byte messages

(with automatic incrementation of the I2C bus sub-

address) as well as repeated Start Condition for

I2C bus subaddress change inside the I2Cbus

messages. All I2C bus registers with specified I2C

bus subaddress are of WRITE ONLY type.

For the I2C bus control register map, refer to chap-

ter I2C BUS CONTROL REGISTER MAP on

page 20.

9.2 SYNC. PROCESSOR

9.2.1 Synchronization signals

The device has two inputs for TTL-level synchroni-

zation signals, both with hysteresis to avoid erratic

detection and with a pull-down resistor. On H/

HVSyn input, pure horizontal or composite hori-

zontal/vertical signal is accepted. On VSyn input,

only pure vertical sync. signal is accepted. Both

positive and negative polarities may be applied on

either input, see Figure 2. Polarity detector and

programmable inverter are provided on each of

the two inputs. The signal applied on H/HVSyn pin,

after polarity treatment, is directly lead to horizon-

tal part and to an extractor of vertical sync. pulses,

working on principle of integration, see Figure 3.

The vertical sync. signal applied to the vertical de-

flection processor is selected between the signal

extracted from the composite signal on H/HVSyn

input and the one applied on VSyn input. The se-

lector is controlled by VSyncSel I2C bus bit.

Besides the polarity detection, the device is capa-

ble of detecting the presence of sync. signals on

each of the inputs and at the output of vertical

sync. extractor. The device is equipped with an au-

tomatic mode (switched on or off by VSyncAuto

I2C bus bit) that uses the detection information.

Normal operation

hysteresis

VCCEn

VCCDis

Disabled

V(Vcc)

VCC

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