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TDA9106A bảng dữ liệu(PDF) 24 Page - STMicroelectronics |
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TDA9106A bảng dữ liệu(HTML) 24 Page - STMicroelectronics |
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24 / 30 page ![]() “ Horizontal Controlled Jitter” on the relative ground of PLL2 capacitor where this “controlled jitter” frequency type will directly affect the horizontal position.The amplitude of the signal is I 2C adjustable. OPERATING DESCRIPTION (continued) One point to notice is : - in case H-Moire is not necessary in the applica- tion, H-Moire output (Pin 2) can be turned to as a 5 bits digital to analog converter output (0.3V to 2.2V V output voltage), - in case of no use in application, this pin must be left high impedance(or resistor to ground). III - VERTICAL PART III.1 - Geometric Corrections The principle is represented in Figure 21. Starting from the vertical ramp, a parabola shaped current is generated for E/W correction, dynamic horizontal phase control correction, and vertical dynamic Focus correction. The base of the parabola generator is an analog multiplier the output current of which is equal to : ∆I= k ⋅ (VOUT -VDCOUT)2 Where Vout is the vertical output ramp, typically comprised between 2 and 5V, Vdcout is the vertical DC output adjustable in the range 3.2V ≥ 3.8V in order to generatea dissymetric parabolaif required (keystone adjustment). Corner and Corner Balance corrections may be added to the E/W one. These are respectively 3rd and 2nd order waveforms. In order to keep a good screen geometry for any end user preferences adjustment we implemented the “geometry tracking”. Due to large output stages voltage range (E/W, FOCUS), the combination of tracking function with maximum vertical amplitude max or min vertical position and maximum gain on the DAC control may lead to the output stages saturation. This must be avoided by limiting the output voltage by apro- priate I 2C registers values. For E/Wpart and Dynamic Horizontal phase control part, a sawtooth shaped differential current in the following form is generated : ∆I’ = k’ ⋅ (VOUT -VDCOUT)2 Then ∆I and ∆I’ are added together and converted into voltage for the E/W part. Each of the four E/W components or the two Dy- namic Horizontal phase control ones may be inhib- ited by their own I 2C select bit. EW Output EW amp Keystone Corner Corner Balance Sidepin amp Parallelogram Vertical Dynamic Focus Output Sidepin Balance Output Current To Horizontal Phase VDCOUT VDCIN 2 VDCOUT VDCOUT VMID Vertical Ramp V OUT Vertical Ramp V OSC 31 32 Figure 21 : Geometric Corrections Principle TDA9106A 24/30 |
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