TLV1544CD datasheet(20/41 Pages) TI

20 / 41 page

TLV1544C, TLV1544I, TLV1548C, TLV1548I, TLV1548M

LOW-VOLTAGE 10-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL AND 4/8 ANALOG INPUTS

SLAS139C – DECEMBER 1996 – REVISED JANUARY 1999

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

td(EOC

↑-CS↓)

NOTE A: To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after CS

↓ before responding to control input

signals. No attempt should be made to clock in input data until the minimum CS setup time elapses.

I/O CLK

Conversion

Sample

(6 I/O CLKs)

EOC

MSB

LSB

Hi-Z

Rise After 10th I/O CLK

↓

(see Note A)

Address Sampled

Initialize State Machine

and Counter

Access

Conversion Starts on 10th I/O CLK

↑

Figure 16. Microprocessor Interface Timing (Normal Sample Mode, INV CLK = High)

NOTE A: To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after CS

↓ before responding to control input

signals. No attempt should be made to clock in input data until the minimum CS setup time has elapsed.

td(EOC

↑-CS↓)

I/O CLK

Conversion

Sample

EOC

MSB

LSB

Hi-Z

Rise After 10th I/O CLK

↓

(see Note A)

Address Sampled

Conversion Starts on 10th I/O CLK

↑

Initialize State Machine

and Counter

(5.5 I/O CLKs)

Access

Figure 17. Microprocessor Interface Timing (Normal Sample Mode, INV CLK = Low)

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