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L9826 bảng dữ liệu(PDF) 12 Page - STMicroelectronics

tên linh kiện L9826
Giải thích chi tiết về linh kiện  Octal Low-Side Driver for Resistive and Inductive Loads with Serial/Parallel Input Control, Output Protection and Diagnostic
PDF  17 Pages
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nhà sản xuất  STMICROELECTRONICS [STMicroelectronics]
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L9826 bảng dữ liệu(HTML) 12 Page - STMicroelectronics

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4 Functional Description
L9826
12/17
CD00002120
4.4
Diagnostics
The output voltage at all outputs is compared with the diagnostic threshold, typ 0,38 · VCC.
Outputs 1 and 2 features dedicated fault latches. The output status signal is filtered and
latched. The fault latches are cleared during NCS low. The latch stores the status bit, so the
first reading after the error occurred might be wrong. The second reading is right.
Table 6.
Diagnostic Table for outputs 1 and 2 in parallel controlled mode:
Fault condition 1) "output short circuit to Vbat" : the output was switched on and the voltage at
the output exceeds the diagnostics threshold. The output operates in current regulation mode
or has been switched off due to thermal shutdown. The status bit is low.
Fault condition 2) "open load" or "output short circuit to GND" : the output is switched off and
the voltage at the output drops below the diagnostics threshold, because the load current is
lower than the output diagnostic current source, the load is interrupted. The diagnostic bit is
low.
For outputs 3 to 8 the output status signals, are fed directly to the SPI register.
Table 7.
Diagnostic Table for outputs 1 to 8 in SPI controlled mode:
The fault condition 1) "output short circuit to Vbat" : the output was switched on and the voltage
at the output exceeded the diagnostics threshold due to overcurrent, the output overload latch
was set and the output has been switched off. The diagnostic bit is high.
Fault condition 2) "open load" or "output short circuit to GND" is the same as of outputs 1 and
2. At the falling edge of NCS the output status data are transferred to the shift register.
When NSC is low, data bits contained in the shift register are transferred to SDO output et
every rising CLK edge.
Output 1, 2
Output-voltage
Status-bit
Output-mode
off
> DG-threshold
high
correct operation
off
< DG-threshold
low
fault condition 2)
on
< DG-threshold
high
correct operation
on
> DG-threshold
low
fault condition 1)
Output 1 ... 8
Output-voltage
Status-bit
Output-mode
off
> DG-threshold
high
correct operation
off
< DG-threshold
low
fault condition 2)
on
< DG-threshold
low
correct operation
on
> DG-threshold
high
fault condition 1)



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