4 Functional Description

L9826

10/17

CD00002120

4

Functional Description

4.1

General

The L9826 integrated circuit features 8 power low-side-driver outputs. Data is transmitted to the

device using the Serial Peripheral Interface, SPI protocol. Outputs 1 and 2 can be controlled

parallel or serial. The power outputs features voltage clamping function for flyback current

recirculation and are protected against short circuit to Vbat.

The diagnostics recognizes two outputs fault conditions: 1) overcurrent for outputs 3 to 8 ,

overcurrent and thermal overload for outputs 1 and 2 in switch-on condition and 2) open load

or short to GND in switch-off condition for all outputs. The outputs status can be read out via

the serial interface.

The chip internal reset is a OR function of the external nRes signal and internally generated

undervoltage nRes signal.

4.2

Output Stages Control

Each output is controlled with its latch and with common reset line, which enables all eight

outputs. Outputs 1 and 2 can be controlled also by its NON1, NON2 inputs. It allows PWM

control independently on the SPI. These inputs features internal pull-up resistors to assure that

the outputs are switched off, when the inputs are open.

The control data are transmitted via the SDI input, the timing of the serial interface is shown in

Figure 4..

The device is selected with low NCS signal and the input data are transferred into the 8 bit shift

register at every falling CLK edge. The rising edge of the NCS latches the new data from the

shift register to the drivers.

Figure 4.

Timing of the Serial Interface

The SPI register data are transferred to the output latch at rising NCS edge. The digital filter

between NCS and the output latch ensures that the data are transferred only after 8 CLK cycles

or multiple of 8 CLK cycles since the last NCS falling edge. The NCS changes only at low CLK.

NCS

CLK

SDI

SDO

tsclch

thclcl

tclh

tcll

tsclcl

thclch

tcsdv

tpcld

tpchdz

not defined

D8

D1

tscld

thcld

D8

D7

D1