M38K09RFS datasheet(222/328 Pages) RENESAS

222 / 328 page

2.11 Clock generating circuit

Rev.2.00

Oct 05, 2006

page 93 of 111

38K0 Group

REJ09B0337-0200

APPLICATION

Fig. 2.11.6 Related registers setting

CPU mode register

(CPUM: address 3B16)

0 : Main clock f(XIN)

b7 b6

0 0 :

φ = f(system clock)/8 (8-divide mode)

0 1 :

φ = f(system clock)/4 (4-divide mode)

1 0 :

φ = f(system clock)/2 (2-divide mode)

1 1 :

φ = f(system clock) (Through mode)

1. Select main clock f(XIN) as system clock and set clock division mode.

USB control register

(USBCON: address 1016)

0 : Main clock f(XIN)

2. Select main clock f(XIN) as USB clock.

PLL control register

(PLLCON: address 0FF816)

3. Enable PLL circuit, and generating PLL output clock (fVCO) 48 MHZ and fSYN.

b4 b3

0 0 : Divided by 8 (fSYN = fUSB/8)

0 1 : Divided by 6 (fSYN = fUSB/6)

1 0 : Divided by 4 (fSYN = fUSB/4)

1 1 : Not selected

b6 b5

0 0 : Not multiplied (fVCO = fXIN)

0 1 : Double (fVCO = fXIN ✕ 2)

1 0 : Quadruple (fVCO = fXIN ✕ 4)

1 1 : Multiplied by 8 (fVCO = fXIN ✕ 8)

1 : PLL enabled

USB control register

(USBCON: address 1016)

1 : fVCO

4. Select PLL output clock (fVCO) as USB clock.

CPU mode register

(CPUM: address 3B16)

1 : fSYN

5. Select fSYN as system clock.

Note: When selecting fSYN as an internal system clock, refer to “2.10 Frequency synthesizer (PLL)” for details

concerning how to generate fUSB (USB clock) from f(XIN) and the notes on PLL circuit.

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