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7477 bảng dữ liệu(PDF) 87 Page - Renesas Technology Corp |
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7477 bảng dữ liệu(HTML) 87 Page - Renesas Technology Corp |
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87 / 354 page ![]() 7470/7471/7477/7478 GROUP USER’S MANUAL 1-70 HARDWARE 1.12 Timers OF OF OF T RL RL RL FF16 (n-1)16 A A A A A A A A A A A A B A A A to B Timer 1 interrupt enable bit Count source (CNTR0 pin) Count period Count period T(s) = 1 ÷ count source frequency ! (the timer initial value + 1) Event counter mode operation example • OF: Overflow • RL: Reload • n: Timer initial value Timer 1 count stop bit Down count Timer 1 interrupt request bit “1” is written “0” is written Count stop Count restart A : • Clearing by writing “0” to the Timer 1 and CNTR interrupt request bits. • Clearing by accepting the Timer 1 and CNTR interrupt requests when the timer 1 and CNTR interrupt enable bits are “1.” Time CNTR interrupt enable bit CNTR interrupt request bit CNTR edge selection bit In this example, the CNTR interrupt request occurs at rising edge of the count source. In this example, each CNTR interrupt request does not occur during executing the CNTR interrupt processing routine. Fig. 1.12.4 Example of event counter mode operation |
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