7477 datasheet(71/354 Pages) RENESAS

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HARDWARE

1.11 Interrupts

7470/7471/7477/7478 GROUP USER’S MANUAL

1-54

Interrupt request occurs

Main routine

Interrupt processing routine

7 to 23 cycles

(At internal system clock

φ = 4 MHz , 1.75 µs to 5.75 µs)

2 cycles

5 cycles

Waiting time for

pipeline post-

processing

Push onto stack

Vector fetch

Interrupt operation starts

0 to 16 cycles

∗

∗: At the DIV instruction executed.

(3) Timing after acceptance of interrupt

The interrupt processing routine starts with the machine cycle after termination of the instruction

being executed.

Figure 1.11.4 shows a processing time up to the execution of the interrupt processing routine and

Figure 1.11.5 shows a timing after acceptance of the interrupt.

Fig. 1.11.4 Processing time up to the execution of interrupt processing routine

Fig. 1.11.5 Timing after acceptance of interrupt

SYNC

Waiting time for

pipeline

postprocessing

Push onto stack

Vector fetch

Interrupt operation starts

Address bus

Data bus

Not used

PCH

PCL

S, SPS

S-2, SPS

S-1, SPS

AL, AH

: CPU operation code fetch cycle

(This is an internal signal which cannot be observed from the external unit.)

: Vector address of each interrupt

: Jump destination address of each interrupt

: “0016” or “01

(when the stack page bit is “0,” SPS is

R/W

SYNC

BL, BH

AL, AH

SPS

“01

0016,” and when the bit is “1,” SPS is

”

”)

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