7470 datasheet(33/361 Pages) RENESAS

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HARDWARE

1.7 Central processing unit (CPU)

7470/7471/7477/7478 GROUP USER’S MANUAL

1-26

1.7.4 Program counter (PC)

The Program counter is a 16-bit counter consisting of an 8-bit register PCH and an 8-bit register PCL. This

counter indicates the address at which the next instruction to be executed is stored.

The contents of this counter are automatically pushed to the stack when a subroutine is called or an

interrupt occurs.

The high-order 8 bits (PCH) of the program counter become the contents of address FFFF16 and the low-

order 8 bits (PCL) become the contents of address FFFE16 immediately after hardware reset.

1.7.5 Processor status register (PS)

The Processor status register is an 8-bit register consisting of 5 flags to indicate the state immediately

after arithmetic processing and 3 flags to determine an operation for the CPU.

Each bit of the Processor status register is described below.

(1) Carry flag (C) ...................................................... Bit 0

The carry flag holds the carry or borrow from the arithmetic logical unit after arithmetic processing.

This flag is also changed by the Shift instruction or Rotate instruction.

This flag is set to “1” by the SEC instruction and cleared to “0” by the CLC instruction.

(2) Zero flag (Z) ........................................................ Bit 1

The zero flag is set to “1” when the arithmetic processing or data transfer result is “0” and cleared

to “0” in all other cases. In the decimal operation mode, this flag is invalidated.

There is no instruction to change the contents of this flag.

(3) Interrupt disable flag (I) ................................... Bit 2

The interrupt request flag disables all instructions (except an interrupt by the BRK instruction). When

this flag is “1,” the interrupt disable state is provided. This flag is set to “1” by accepting an interrupt,

thereby disabling a multi-interrupt.

This flag is set to “1” by the SEI instruction and cleared to “0” by the CLI instruction.

This flag is set to “1” (interrupt disable state) immediately after hardware reset.

(4) Decimal mode flag (D) ...................................... Bit 3

The decimal mode flag determines whether addition and subtraction should be performed in binary

or decimal notation. When the contents of this flag are “0,” an ordinary binary operation is performed.

When they are “1,” an arithmetic operation is performed assuming that one word is a 2-digit decimal

number. In a decimal operation, decimal compensation is automatically performed (decimal operation

can be performed only by the ADC instruction and the SBC instruction).

This flag is set to “1” by the SED instruction and cleared to “0” by the CLD instruction.

This flag is put in an undefined state immediately after hardware reset. As this flag directly affects

arithmetic operations, be sure to initialize it.

(5) Break flag (B) ...................................................... Bit 4

The break flag identifies whether or not an interrupt has been caused by the BRK instruction. The

BRK instruction is used for program debugging and performs the same operation as an interrupt is

performed by executing the BRK instruction.

The Processor status register is pushed to the stack, after the B flag is automatically set to “1” in

case of the BRK instruction interrupt, or after the B flag is automatically cleared to “0” in case of the

other interrupts.

There is no instruction to change the contents of this flag.

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