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7470 bảng dữ liệu(PDF) 32 Page - Renesas Technology Corp |
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7470 bảng dữ liệu(HTML) 32 Page - Renesas Technology Corp |
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32 / 361 page ![]() 7470/7471/7477/7478 GROUP USER’S MANUAL HARDWARE 1.7 Central processing unit (CPU) 1-25 Fig. 1.7.2 Register push and pop at interrupt generation and subroutine call Note : Condition for acceptance of an interrupt • • • Interrupt disable flag is “0” (enable state) Interrupt enable bit is “1” (enable state) On-going routine • • • • • • • • • • • • • • • • • • M(S) (PCH) (S) (S)–1 M(S) (PCL) (S) (S)–1 (S) (S)+1 (PCL) M(S) (S) (S)+1 (PCH) M(S) (PCH) M(S) (S) (S)+1 (PCL) M(S) (S) (S)+1 (PS) M(S) (S) (S)+1 Interrupt Service Routine (S) (S)–1 M(S) (PS) (S) (S)–1 M(S) (PCL) (S) (S)–1 M(S) (PCH) Execute JSR Execute RTI • • • Push return address on stack Pop return address from stack Pop contents of Processor status register from stack Pop return address from stack Push contents of Processor status register on stack Push return address on stack When a subroutine is called When an interrupt is accepted Interrupt request (Note) I Flag is set from “0” to “1” Fetch the Jump Vector : Operation which is automatically performed by hardware : Operation instructed by software Subroutine Execute RTS • • • |
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