7905 datasheet(59/565 Pages) RENESAS

59 / 565 page

RESET

7905 Group User’s Manual Rev.1.0

3-14

3.3 State of internal area

000

(Note 20)

A-D register 9

A-D register 11

A-D register 10

A-D register 8

(Note 19)

UART2 transmit interrupt control register

UART2 receive interrupt control register

000

(Note 20)

Address

Access characteristics

State immediately after reset

Timer A5 interrupt control register

Timer A7 interrupt control register

Timer A8 interrupt control register

Timer A9 interrupt control register

Timer A6 interrupt control register

INT7 interrupt control register

INT6 interrupt control register

INT5 interrupt control register

Notes 19: The access characteristics at addresses E016 to E716 vary according to the contents of the comparator function

select register 1 (address DD16). (Refer to “CHAPTER 12. A-D CONVERTER.”)

20: Do not write to this register.

E016

E116

E216

E316

E416

E516

E616

E716

E816

E916

F016

F116

F216

F316

F416

F516

F616

F716

F816

F916

FA16

FB16

FC16

FD16

FE16

FF16

EB16

EC16

ED16

EE16

EF16

EA16

q Internal RAM area

At hardware reset ................................................................................. Retains the state immediately before reset (Note 21).

At software reset.................................................................................................... Retains the state immediately before reset.

At termination of the stop or wait mode

(when hardware reset is used for the termination.)....................................Retains the state immediately before the STP or

WIT instruction is executed.

At power-on reset..................................................................................................................................................... Undefined.

Notes 21 : When a reset operation starts while writing to the internal RAM area is in process, the microcomputer will be

reset before the completion of writing. Accordingly, the contents of the area where the writing was in process

will become undefined.

Fig. 3.3.9 State of SFR and internal RAM areas immediately after reset (8)

7905 bảng dữ liệu(PDF) 59 Page - Renesas Technology Corp

7905 bảng dữ liệu(HTML) 59 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL