7721 datasheet(314/577 Pages) RENESAS

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DMA CONTROLLER

7721 Group User’s Manual

13-35

13.4 Operation

Tables 13.4.3 Address directions in 2-bus cycle transfer and examples of transfer result (2)

Note: The position relationship between low-

order byte and high-order byte is not

reversed.

Transfer unit : 8 bits

Address direction

Transfer

source

Transfer unit : 16 bits

Transfer

sequence

External data bus width : 16 bits or 8 bits

Transfer

destination

Data arrangement

on transfer source

memory

Data arrangement

on transfer source

memory

Data arrangement on

transfer destination

memory (transfer result)

Transfer

sequence

Data arrangement on

transfer destination

memory (transfer result)

Forward

Fixed

Forward

Backward

Data 1

Low order

High order

Data 2

Low order

High order

Data 3

Low order

High order

Data

1–3

Low order

High order

Data 1

Data 2

Data 3

Data 4

Data 5

Data 6

Data 1–6

Data 1

Low order

High order

Data 2

Low order

High order

Data 3

Low order

High order

Data 1

Low order

High order

Data 2

Low order

High order

Data 3

Low order

High order

Data 1

Data 2

Data 3

Data 4

Data 5

Data 6

Data 1

Data 2

Data 3

Data 4

Data 5

Data 6

Data 1

Data 2

Data 3

Data 4

Data 5

Data 6

Data 5

Data 4

Data 3

Data 2

Data 1

Data 2

Data 3

Low order

High order

Low order

High order

Low order

High order

Data 3

Data 2

Data 1

Low order

High order

Low order

High order

Low order

High order

V : Transfer start address

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