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7721 bảng dữ liệu(PDF) 308 Page - Renesas Technology Corp |
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7721 bảng dữ liệu(HTML) 308 Page - Renesas Technology Corp |
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308 / 577 page  7721 Group User’s Manual 13-29 DMA CONTROLLER 13.3 Control Fig.13.3.4 States of SARi, DARi, TCRi after forced termination Previously written values Latch Register Transfer source/destination address is specified. Contents are updated by incrementer/decrementer and decrementer. a. State at forced termination b. When setting DMAi enable bit to “1” without rewriting values at addresses of SARi, DARi, and TCRi A value read from each latch is used by hardware only at the first 1-unit transfer. The contents updated by the incrementer/decrementer and the decrementer are loaded in each register. Values are used by reading them from registers at the second and the following 1-unit transfers. Latch Register Previously written values Updated contents are written. c. When reading values at addresses of SARi, DARi, and TCRi after forced termination and rewriting them Latch Register Previously written values Written by software Read by software Addresses which were to be transferred subsequently or the number of remaining bytes Addresses which were to be transferred subsequently or the number of remaining bytes Addresses which were to be transferred subsequently or the number of remaining bytes Addresses which were to be transferred subsequently or the number of remaining bytes |
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