7721 datasheet(211/577 Pages) RENESAS

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SERIAL I/O

7721 Group User’s Manual

11–8

(1)

Transmit enable bit (bit 0)

By setting this bit to “1,” UARTi enters the transmission enable state. By clearing this bit to “0” during

transmission, UARTi enters the transmission disable state after the transmission which is in progress

at that time is completed.

(2)

Transmit buffer empty flag (bit 1)

This flag is set to “1” when data set in the UARTi transmit buffer register is transferred from the

UARTi transmit buffer register to the UARTi transmit register. This flag is cleared to “0” when data

is set in the UARTi transmit buffer register.

(3)

Receive enable bit (bit 2)

By setting this bit to “1,” UARTi enters the reception enable state. By clearing this bit to “0” during

reception, UARTi quits the reception immediately and enters the reception disable state.

(4)

Receive complete flag (bit 3)

This flag is set to “1” when data is ready in the UARTi receive register and that is transferred to the

UARTi receive buffer register (i.e., when reception is completed). This flag is cleared to “0” when one

of the following is performed:

•Reading the low-order byte of the UARTi receive buffer register out

•Clearing the receive enable bit (bit 2) to “0”

•Clearing the serial I/O mode select bits (bits 2 to 0 at addresses 3016, 3816) to “0002.”

11.2 Block description

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