7220 datasheet(85/303 Pages) RENESAS

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7220 Group User’s Manual

FUNCTIONAL DESCRIPTION

2.8 Multi-master I2C-BUS interface

(1)

START condition generation method

When the ESO bit of the I2C control register (address 00DA16) is “1,” execute a write instruction to

the I2C status register (address 00D916) to set the MST, TRX and BB bits to “1.” A START condition

will then be generated. After that, the bit counter becomes “0002” and an SCL for 1 byte is output.

The START condition generating timing and BB bit set timing are different in the standard clock mode

and the high-speed clock mode. Refer to “Figure 2.8.9” for the START condition generation timing

diagram, and “Table 2.8.2” for the START condition/STOP condition generation timing table.

(2)

STOP condition generation method

When the ESO bit of the I2C control register (address 00DA16) is “1,” execute a write instruction to

the I2C status register (address 00D916) for setting the MST bit and the TRX bit to “1” and the BB

bit to “0”. A STOP condition will then be generated. The STOP condition generation timing and the

BB flag reset timing are different in the standard clock mode and the high-speed clock mode. Refer

to “Figure 2.8.10” for the STOP condition generating timing diagram, and “Table 2.8.2” for the

START condition/STOP condition generation timing table.

2.8.3 START condition, STOP condition generation method

Fig. 2.8.9 START condition generation timing diagram

I2C status register

write signal

Set time for

BB flag

Hold time

Setup

time

SCL

SDA

BB flag

Setup

time

Fig. 2.8.10 STOP condition generation timing diagram

I2C status register

write signal

Reset time for

BB flag

Hold time

Setup

time

SCL

SDA

BB flag

Item

Setup time

Hold time

Set/reset time for BB flag

High-speed clock mode

2.5

µ s (10 cycles)

2.5

µ s (10 cycles)

1.5

µ s (6 cycles)

Standard clock mode

5.0

µ s (20 cycles)

5.0

µ s (20 cycles)

3.0

µ s (12 cycles)

Note: Absolute time at

f = 4 MHz.

The value in parentheses denotes the number of

f cycles.

Table 2.8.2 START condition/STOP condition generation timing table

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