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7220 Group User’s Manual

FUNCTIONAL DESCRIPTION

2.5 Interrupts

(7)

Timer 3 interrupt

Timer 3 value is counted down. Timer 3 interrupt request occurs when the count source next to “0016”

is input.

(8)

Timer 2 interrupt

Timer 2 value is counted down. Timer 2 interrupt request occurs when a count source next to “0016”

is input

(9)

Timer 1 interrupt

Timer 1 value is counted down. Timer 1 interrupt request occurs when a count source next to “0016”

is input.

(10) Serial I/O interrupt

The serial I/O interrupt request is generated by detecting a rising edge of the eighth serial transfer

clock after writing to the serial I/O register.

(11) Multi-master I2C-BUS interface interrupt

A multi-master interrupt request occurs synchronized with a falling edge serial clock (SCL) every

completion of 1-byte data communication.

(12) INT3 interrupt

An INT3 interrupt request is generated by detecting a transition in the level on pin INT3 (external

interrupt input).

Detecting either positive polarity (LOW to HIGH transition) or negative polarity (HIGH to LOW transition)

to be detected is set with RE5 (the interrupt input polarity register: bit 5 at address 00F916). When

RE5 is set to “0,” a positive polarity is detected, when RE5 is set to “1,” a negative polarity is

detected.

Pin INT3 is also used for port P15 and pin A-D1. An INT3 interrupt by a level transition on the pin

may cause software runaway. Therefore, when this pin is used as port P15, disable an INT3 interrupt

by using an interrupt enable bit and interrupt disable flag (1).

(13) BRK instruction interrupt

This software interrupt has the least significant priority and generates an interrupt request is generated

by executing when the BRK instruction. There is no corresponding interrupt enable bit and no

influence by the interrupt disable flag (I).

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