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SH7713 bảng dữ liệu(PDF) 173 Page - Renesas Technology Corp

tên linh kiện SH7713
Giải thích chi tiết về linh kiện  Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
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Section 3 DSP Operating Unit
Rev.1.50 Aug. 30, 2006 Page 133 of 860
REJ09B0288-0150
39
31
39
31
0
0
Cleared to 0
Priority encoder
Source 1 or 2
DSR
GT
Z
N
V
DC
Guard
Guard
Figure 3.19 PDMSB Operation Flow
The definition of the DC bit is selected by the CS0–CS2 (condition selection) bits in DSR. The
DC bit result is
Carry or Borrow Mode: CS[2:0] = 000: The DC bit is always cleared.
Negative Value Mode: CS[2:0] = 001: The DC bit is set when the operation result is a negative
value, and cleared when the operation result is zero or a positive value.
Zero Value Mode: CS[2:0] = 010: The DC bit is set when the operation result is zero; otherwise
it is cleared.
Overflow Mode: CS[2:0] = 011: The DC bit is always cleared.
Signed Greater Than Mode: CS[2:0] = 100: The DC bit is set when the operation result is a
positive value; otherwise it is cleared.
Signed Greater Than or Equal Mode: CS[2:0] = 101: The DC bit is set when the operation
result is zero or a positive value; otherwise it is cleared.



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