SH7713 datasheet(139/904 Pages) RENESAS

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Section 3 DSP Operating Unit

Rev.1.50 Aug. 30, 2006 Page 99 of 860

REJ09B0288-0150

3.4.2

DSP Data Addressing

Table 3.10 shows the relationship between the double data transfer instructions and single data

transfer instructions.

Table 3.10

Overview of Data Transfer Instructions

Double Data Transfer Instructions Single Data Transfer Instructions

MOVX.W

MOVY.W

MOVS.W

MOVS.L

Address register

Ax: R4, R5,

Ay: R6, R7

As: R2, R3, R4, R5

Index register

Ix: R8, Iy: R9

Is: R8

Addressing

Nop/Inc (+2)/index addition:

post-increment

Nop/Inc (+2, +4)/index addition:

post-increment

Addressing

—

Dec (–2, –4): pre-decrement

Modulo addressing

Possible

Not possible

Data bus

XDB, YDB

LDB

Data length

16 bits (word)

16/32 bits (word/longword)

Bus conflict

Yes

Memory

X/Y data memory

Entire memory space

Source register

Dx, Dy: A0, A1

Ds: A0/A1, M0/M1, X0/X1, Y0/Y1,

A0G, A1G

Destination register

Dx: X0/X1

Dy: Y0/Y1

Ds: A0/A1, M0/M1, X0/X1, Y0/Y1,

A0G, A1G

Addressing Mode for Double Data Transfer Instructions: The double data transfer instructions

supports the following three addressing modes.

• Non-update address register addressing

The Ax and Ay registers are address pointers. They are not updated.

• Increment address register addressing

The Ax and Ay registers are address pointers. After a data transfer, they are each incremented

by 2 (post- increment).

• Addition index register addressing

The Ax and Ay registers are address pointers. After a data transfer, the value of the Ix or Iy

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