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SH7713 bảng dữ liệu(PDF) 116 Page - Renesas Technology Corp

tên linh kiện SH7713
Giải thích chi tiết về linh kiện  Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
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Section 3 DSP Operating Unit
Rev.1.50 Aug. 30, 2006 Page 76 of 860
REJ09B0288-0150
• In privileged and privileged DSP modes, all SR bits can be modified.
• In user DSP mode, the SR can be read by the STC instruction.
• In user DSP mode, the LDC instruction can be issued to the SR but only the DSP extension
bits can be modified.
Table 3.2
Operation of SR Bits in Each Processing Mode
Privileged
Mode
User Mode
Privileged
DSP Mode
User DSP
Mode
Field
MD = 1 &
DSP = 0
MD = 0 &
DSP = 0
MD = 1 &
DSP = 1
MD = 0 &
DSP = 1
Access to
DSP-Related
Bit with
Dedicated
Instruction
Initial Value
after Reset
MD
S: OK, L: OK
S, L: Invalid
instruction
S: OK, L: OK
S: OK, L: NG
1
RB
S: OK, L: OK
S, L: Invalid
instruction
S: OK, L: OK
S: OK, L: NG
1
BL
S: OK, L: OK
S, L: Invalid
instruction
S: OK, L: OK
S: OK, L: NG
1
RC
[11:0]
S: OK, L: OK
S, L: Invalid
instruction
S: OK, L: OK
S: OK, L: OK
SETRC
instruction
000000000000
DSP
S: OK, L: OK
S, L: Invalid
instruction
S: OK, L: OK
S: OK, L: NG
0
DMY
S: OK, L: OK
S, L: Invalid
instruction
S: OK, L: OK
S: OK, L: OK
0
DMX
S: OK, L: OK
S, L: Invalid
instruction
S: OK, L: OK
S: OK, L: OK
0
Q
S: OK, L: OK
S, L: Invalid
instruction
S: OK, L: OK
S: OK, L: NG
x
M
S: OK, L: OK
S, L: Invalid
instruction
S: OK, L: OK
S: OK, L: NG
x
I[3:0]
S: OK, L: OK
S, L: Invalid
instruction
S: OK, L: OK
S: OK, L: NG
1111
RF[1:0]
S: OK, L: OK
S, L: Invalid
instruction
S: OK, L: OK
S: OK, L: OK
SETRC
instruction
x
S
S: OK, L: OK
S, L: Invalid
instruction
S: OK, L: OK
S: OK, L: NG
x
T
S: OK, L: OK
S, L: Invalid
instruction
S: OK, L: OK
S: OK, L: NG
x
[Legend]
S:
STC instruction
L:
LDC instruction
OK:
STC/LDC operation is enabled.
Invalid instruction:
Exception occurs when an invalid instruction is executed.
NG:
Previous value is retained. No change.
x:
Undefined



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