SH7713 datasheet(511/904 Pages) RENESAS

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Section 13 Direct Memory Access Controller (DMAC)

Rev.1.50 Aug. 30, 2006 Page 471 of 860

REJ09B0288-0150

13.3.6

DMA Extension Resource Selector 0 to 2 (DMARS0 to DMARS2)

DMARS is a 16-bit readable/writable register that specifies the DMA transfer sources from

peripheral modules in each channel. DMARS0 specifies for channels 0 and 1, DMARS1 specifies

for channels 2 and 3, and DMARS2 specifies for channels 4 and 5. This register can set the

transfer requests of the SCIF0, SCIF1, SIOF0, and SIOF1.

When MID and RID other than the values listed in table 13.2 are set, the operation of this LSI is

not guaranteed. The transfer request from DMARS is valid only when bits RS3 to RS0 has been

set to B'1000 in CHCR0 to CHCR5. Otherwise, even if DMARS has been set, a transfer request

source is not accepted.

DMARS is initialized to H'0000 at reset and retains the current value in standby or module

standby mode.

• DMARS0

Bit

Bit Name

Initial

Value

R/W

Description

C1MID5

C1MID4

C1MID3

C1MID2

C1MID1

C1MID0

R/W

Transfer request module ID for DMA channel 1 (MID)

See table 13.2.

C1RID1

C1RID0

R/W

Transfer request register ID for DMA channel 1 (RID)

See table 13.2.

C0MID5

C0MID4

C0MID3

C0MID2

C0MID1

C0MID0

R/W

Transfer request module ID for DMA channel 0 (MID)

See table 13.2.

C0RID1

C0RID0

R/W

Transfer request register ID for DMA channel 0 (RID)

See table 13.2.

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