SH7713 datasheet(504/904 Pages) RENESAS

504 / 904 page

Section 13 Direct Memory Access Controller (DMAC)

Rev.1.50 Aug. 30, 2006 Page 464 of 860

REJ09B0288-0150

13.3.3

DMA Transfer Count Register (DMATCR)

DMATCR is a 32-bit readable/writable registers that specifies the DMA transfer count. The

number of transfers is 1 when the setting is H'00000001, 16,777,215 when H'00FFFFFF is set, and

16,777,216 (the maximum) when H'00000000 is set. During a DMA transfer, DMATCR indicates

the remaining transfer count.

The upper eight bits of DMATCR will return 0 if read, and should only be written with 0.

To transfer data in 16 bytes, one 16-byte transfer (128 bits) counts one.

DMATCR is undefined at reset and retains the current value in standby or module standby mode.

13.3.4

DMA Channel Control Register (CHCR)

CHCR is a 32-bit readable/writable register that controls the DMA transfer mode.

CHCR is initialized to H'00000000 at reset and retains the current value in the standby or module

standby mode.

Bit

Bit Name

Initial

Value

R/W

Description

31 to



All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

R/W

DMA Overrun

Selects whether the DREQ is detected by overrun 0 or by

overrun 1.

This bit is valid only in CHCR0 and CHCR1.This bit is

reserved and always read as 0 in CHCR2 to CHCR5. The

write value should always be 0.

0: Detects DREQ by overrun 0

1: Detects DREQ by overrun 1

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