SH7713 datasheet(461/904 Pages) RENESAS

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Section 12 Bus State Controller (BSC)

Rev.1.50 Aug. 30, 2006 Page 421 of 860

REJ09B0288-0150

Single Write: A write access ends in one cycle when data is written in non-cachable region and

the data bus width is larger than or equal to access size.

Figure 12.18 shows the single write basic timing.

CKIO

A25 to A0

CSn

RD/

RAS

DQMxx

D31 to D0

Tap

DACKn*2

Tc1

Trwl

A12/A11*1

CAS

Notes: 1. Address pin to be connected to the A10 pin of SDRAM.

2. The waveform for DACKn is when active low is specified.

Figure 12.18 Basic Timing for Single Write (Auto-Precharge)

Bank Active: The synchronous DRAM bank function is used to support high-speed accesses to

the same row address. When the BACTV bit in SDCR is 1, accesses are performed using

commands without auto-precharge (READ or WRIT). This function is called bank-active function.

This function is valid only for either the upper or lower bits of area 3. When area 3 is set to bank-

active mode, area 2 should be set to normal space or byte-selection SRAM. When areas 2 and 3

are both set to SDRAM, auto precharge mode must be set.

When a bank-active function is used, precharging is not performed when the access ends. When

accessing the same row address in the same bank, it is possible to issue the READ or WRIT

command immediately, without issuing an ACTV command. As synchronous DRAM is internally

divided into several banks, it is possible to activate one row address in each bank. If the next

access is to a different row address, a PRE command is first issued to precharge the relevant bank,

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