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SH7713 bảng dữ liệu(PDF) 431 Page - Renesas Technology Corp

tên linh kiện SH7713
Giải thích chi tiết về linh kiện  Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
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Section 12 Bus State Controller (BSC)
Rev.1.50 Aug. 30, 2006 Page 391 of 860
REJ09B0288-0150
read in case of a 32-bit device, and 16 bits in case of a 16-bit device. When writing, only the
WEn
(
BEn) signal for the byte to be written is asserted.
It is necessary to output the data that has been read using
RD when a buffer is established in the
data bus. The RD/
WR signal is in a read state (high output) when no access has been carried out.
Therefore, care must be taken when controlling the external data buffer, to avoid collision.
Figures 12.4 and 12.5 show the basic timings of normal space accesses. If the WM bit of the
CSnWCR is cleared to 0, a Tnop cycle is inserted to evaluate the external wait (figure 12.4). If the
WM bit of the CSnWCR is set to 1, external waits are ignored and no Tnop cycle is inserted
(figure 12.5).



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