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SH7713 bảng dữ liệu(PDF) 399 Page - Renesas Technology Corp

tên linh kiện SH7713
Giải thích chi tiết về linh kiện  Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
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nhà sản xuất  RENESAS [Renesas Technology Corp]
Trang chủ  http://www.renesas.com
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SH7713 bảng dữ liệu(HTML) 399 Page - Renesas Technology Corp

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Section 12 Bus State Controller (BSC)
Rev.1.50 Aug. 30, 2006 Page 359 of 860
REJ09B0288-0150
Bit
Bit Name
Initial
Value
R/W
Description
5 to 2
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
1
0
HW1
HW0
0
0
R/W
R/W
Number of Delay Cycles from
RD, WEn (BEn) negation to
Address,
CSn negation
Specify the number of delay cycles from
RD and WEn
(
BEn) negation to address and CSn negation.
00: 0.5 cycle
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
• CS5BWCR
Bit
Bit Name
Initial
Value
R/W
Description
31 to
21
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
20
BAS
0
R/W
Byte Access Selection for Byte-Selection SRAM
Specifies the
WEn (BEn) and RD/WR signal timing when
the byte-selection SRAM interface is used.
0: Asserts the
WEn (BEn) signal at the read/write timing
and asserts the RD/
WR signal during the write access
cycle.
1: Asserts the
WEn (BEn) signal during the read/write
access cycle and asserts the RD/
WR signal at the write
timing.
19
0
R
Reserved
This bit is always read as 0. The write value should always
be 0.



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