M16CSLASH62M datasheet(262/615 Pages) RENESAS

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Appendix Standard Serial I/O Mode 1 (Flash Memory Version)

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

1-243

Clear Status Register Command

This command clears the bits (SR3–SR5) which are set when the status register operation ends in

error. When the “5016” command code is sent with the 1st byte, the aforementioned bits are cleared.

When the clear status register operation ends, the RTS1 (BUSY) signal changes from the “H” to the

“L” level.

Figure 1.29.5. Timing for clearing the status register

Page Program Command

This command writes the specified page (256 bytes) in the flash memory sequentially one byte at a

time. Execute the page program command as explained here following.

(1) Transfer the “4116” command code with the 1st byte.

(2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively.

(3) From the 4th byte onward, as write data (D0–D7) for the page (256 bytes) specified with addresses

A8 to A23 is input sequentially from the smallest address first, that page is automatically written.

When reception setup for the next 256 bytes ends, the RTS1 (BUSY) signal changes from the “H” to

the “L” level. The result of the page program can be known by reading the status register. For more

information, see the section on the status register.

Each block can be write-protected with the lock bit. For more information, see the section on the data

protection function. Additional writing is not allowed with already programmed pages.

Figure 1.29.6. Timing for the page program

CLK1

RxD1

TxD1

RTS1(BUSY)

5016

(M16C reception data)

(M16C transmit data)

CLK1

RxD1

TxD1

RTS1(BUSY)

A8 to

A15

A16 to

A23

4116

data0

data255

(M16C reception data)

(M16C transmit data)

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