M16CSLASH62M datasheet(168/615 Pages) RENESAS

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Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

A-D Converter

1-149

Item

Performance

Method of A-D conversion Successive approximation (capacitive coupling amplifier)

Analog input voltage (Note 1) 0V to AVCC (VCC)

Operating clock

φAD (Note 2) VCC = 5V

fAD/divide-by-2 of fAD/divide-by-4 of fAD, fAD=f(XIN)

VCC = 3V

divide-by-2 of fAD/divide-by-4 of fAD, fAD=f(XIN)

Resolution

8-bit or 10-bit (selectable)

Absolute precision

VCC = 5V

• Without sample and hold function

±3LSB

• With sample and hold function (8-bit resolution)

±2LSB

• With sample and hold function (10-bit resolution)

AN0 to AN7 input :

±3LSB

ANEX0 and ANEX1 input (including mode in which external

operation amp is connected) :

±7LSB

VCC = 3V

• Without sample and hold function (8-bit resolution)

±2LSB

Operating modes

One-shot mode, repeat mode, single sweep mode, repeat sweep mode 0,

and repeat sweep mode 1

Analog input pins

8pins (AN0 to AN7) + 2pins (ANEX0 and ANEX1)

A-D conversion start condition • Software trigger

A-D conversion starts when the A-D conversion start flag changes to “1”

• External trigger (can be retriggered)

A-D conversion starts when the A-D conversion start flag is “1” and the

___________

ADTRG/P97 input changes from “H” to “L”

Conversion speed per pin • Without sample and hold function

8-bit resolution: 49

φAD cycles, 10-bit resolution: 59 φAD cycles

• With sample and hold function

8-bit resolution: 28

φAD cycles, 10-bit resolution: 33 φAD cycles

A-D Converter

The A-D converter consists of one 10-bit successive approximation A-D converter circuit with a capacitive coupling

amplifier. Pins P100 to P107, P95, and P96 also function as the analog signal input pins. The direction registers of

these pins for A-D conversion must therefore be set to input. The Vref connect bit (bit 5 at address 03D716) can be

used to isolate the resistance ladder of the A-D converter from the reference voltage input pin (VREF) when the A-D

converter is not used. Doing so stops any current flowing into the resistance ladder from VREF, reducing the power

dissipation. When using the A-D converter, start A-D conversion only after setting bit 5 of 03D716 to connect VREF.

The result of A-D conversion is stored in the A-D registers of the selected pins. When set to 10-bit precision, the low

8 bits are stored in the even addresses and the high 2 bits in the odd addresses. When set to 8-bit precision, the low

8 bits are stored in the even addresses.

Table 1.17.1 shows the performance of the A-D converter. Figure 1.17.1 shows the block diagram of the

A-D converter, and Figures 1.17.2 and 1.17.3 show the A-D converter-related registers.

Note 1: Does not depend on use of sample and hold function.

Note 2: Divide the frequency if f(XIN) exceeds 10MHZ, and make

φAD frequency equal to or less than 10MHz.

Without sample and hold function, set the

φAD frequency to 250kHZ min.

With the sample and hold function, set the

φAD frequency to 1MHZ min.

Table 1.17.1. Performance of A-D converter

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